As data rates continue to increase, it is becoming increasingly difficult to match the data and timing signal lines to eliminate timing skews. Using a dedicated time signal line to be routed along with the data lines is costly in terms of chip area and power. Thus, in a high speed SERDES link, a clock data recovery (CRD) circuit is commonly used on the receiver to align a sampling clock with incoming data adaptively. Such a CDR circuit only utilizes the data signal itself to determine when to sample the signal to reliably extract the data, and therefore a time line is no longer needed from the link. By virtue of clock recovery, a CDR circuit can synchronize a receiver clock with the transmitter clock generated for the signal. And by virtue of phase selection, a CDR circuit can select a phase with respect to the receiver clock at which to sample the received signal in order to provide a good signal-to-noise ratio (SNR) for accurate data recovery.
The Peripheral Component Interconnect Express (PCIe) 3.0 architecture adopts the encoding scheme of 128b/130b, where a data block can include 2 bits synchronization header followed by 128 bits scrambled payload. A SKP ordered sets can be used to compensate for differences in frequencies between bit rates at two ends of a link. In a typical data block, data are transmitted in the form of a pseudo random binary sequence (PRBS) following a SKP pattern. Hence, at the receiver side, not only the PRBS bits are received, but also the SKP ordered set bits are received in clock pattern. FIG. 1 is a table listing the values of the SKP ordered sets used for equalization in a high speed series link in compliance with the Based Specification for PCIe 3.0.
A conventional CDR circuit essentially comprises a phase frequency detector (PFD) coupled to a voltage controlled oscillator (VCO) through a low pass filter (LPF), and optionally through an up/down counter. The PFD can detect a phase frequency difference between an input data and a feedback signal recovered clock (e.g. a recovered clock) that samples the input data in the CDR loop and generate a phase error signal accordingly. The phase error signal, after filtered through the LPF and converted to a control voltage, controls the oscillating output frequency of the VCO which is also the output of the CDR loop so as to minimize the phase difference between the input signal and the output signal of the CDR loop.
In the context of data transmission based on PCIe 3.0, the input signal may include a clock pattern and a PRBS pattern. It has been observed that a CDR often locks at different phase for these two patterns. FIG. 2 is a phase diagram depicting the transient simulation of CDR locked phases when a Modified Compliance Pattern (MCP) that passes a PCIe 3.0 RX (receiver) compliance test channel and is fed to a CDR circuit in accordance with the prior art. The data plot 200 simulates an output of a phase interpolator in the CDR circuit in response to the MCP which includes PRBS bits and SKP pattern as defined in the Based Specification of PCIe 3.0. The plot for the time periods 201 and 203 represents the PRBS locked phases that fluctuate in a small range and with an average of 29 (a.u.). In contrast, the plot for the time period 202 represents the locked phases for the clock pattern with a valley of 21 (a.u.). As illustrated, the data plot 200 demonstrates that the CDR phase can be abruptly dragged down from a PRBS locked phase to a remarkably lower locked phase for the clock pattern.
Generally speaking, due to the inherently unequal propagation delays for the two inputs of the phase detector, most phase detectors that operate properly with random data are asymmetric with respect to the data and clock inputs, thereby introducing a systematic skew between the two in phase lock condition. When receiving a PRBS signal, the CDR typically produces a sampling clock at the midpoint in the data eye. The significant phase shift in response to the transitions between a PRBS and a clock pattern can cause a sampling clock of the CDR to shift by 10% UI, resulting in loss of timing margin for clock data recovery by 10%.